De MEMRISTOR nieuw fundamenteel component

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Op zondag 21 maart 2010 19:45 schreef Refragmental het volgende:
http://www.youtube.com/us(...)638C02/3/Z5UTRTOfgo4

In deze lezing uit de OP wordt uitgelegd hoe ze de memristor bovenop de huidige transistor kunnen plaatsen, en niet 1,2 of 3 lagen maar mogelijk duizend lagen.

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Op maandag 22 maart 2010 13:41 schreef Onverlaatje het volgende:
Maar als ik het goed begrijp kan er nu wel een specifiek neuraal netwerk CPU gemaakt worden.
Wat zouden de toepassingen van dergelijke CPU's zijn in het dagelijks leven?
Verbeterde database searches? Een just in time compiler, gebakken in de CPU zelf?

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Op maandag 22 maart 2010 18:00 schreef Onverlaatje het volgende:

Dan zou er een compiler configuration interface geschreven dienen te worden, zodat een CPU kan vertellen wat de logica achter de instructies is.

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Op maandag 22 maart 2010 21:46 schreef Onverlaatje het volgende:

De oplossing is dan dat een bytecode compiler generieke (tussen verschillende processoren) code voor te laten compileren naar generieke machinecode en tussen deze code blokken bytecode aan te geven welke hercompileert dienen te worden naar CPU specifieke instructiesets. Zo kan je bedrijfsgevoelige code verdelen tussen blokken processorgenerieke code en te optimaliseren bytecode en zo dus 'obfuscaten' terwijl je wel geoptimaliseerde code laat uitvoeren.

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Op maandag 22 maart 2010 22:38 schreef YuckFou het volgende:

Ik heb sterk het idee dat je hier de transistor sterk tekort mee doet

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Siliciumgeheugen maakt kleiner productieprocedé eenvoudig

Door Willem de Moor, woensdag 1 september 2010 14:13, views: 1.597

De volgende stap naar nog kleinere productieprocedés zou dankzij siliciumgeheugen vrij eenvoudig zijn. Onderzoekers hebben eenvoudige geheugencellen ontwikkeld, die slechts bestaan uit silicium en aansluitingen.

Het nieuwe type geheugen werd ontwikkeld na observaties van dunne stroken grafiet, van ongeveer tien nanomoeter breed. Onder invloed van een stroompuls kon de strook worden gebroken en weer verbonden, wat het equivalent van een geheugenbit vormde. Nader onderzoek wees echter uit dat dit effect niet afhankelijk is van grafiet; ook silicium vertoont dit fenomeen. Aangezien silicium het hoofdbestanddeel van vrijwel alle processors is en goed in halfgeleiderproducten kan worden verwerkt, zou het siliciumgeheugen snel in productieprocessen kunnen worden geïntegreerd.

Het siliciumgeheugen werkt door een laagje siliciumoxide, een elektrische isolator, tussen twee lagen geleidend polykristallijn silicium te klemmen. Bij het aanbrengen van een stroom worden oxide-atomen van het silicium gestript, wat zorgt voor de vorming van geleidende siliciumkristallen. Eenmaal gevormd kunnen deze kristalsporen, net als het grafiet eerder, steeds opnieuw worden verbonden en verbroken. De lagen 'poly' dienen hierbij als elektrodes. Flashgeheugen is complexer en heeft drie elektrodes nodig.

De zo gevormde geheugenbits kunnen bijzonder eenvoudig worden geproduceerd en gezien hun samenstelling laten zij zich eenvoudig in bijvoorbeeld processors verwerken. Bovendien zijn de structuren zeer klein. De kristaldraden zijn tussen de vijf en tien nanometer groot, veel kleiner dan de featuresize waaraan de huidige geheugenproductietechnieken met hun 20 tot 30nm toe zijn. De siliciumoxide-geheugenbits zijn tevens in driedimensionale structuren te stapelen en schakelen in minder dan 100ns. De onderzoekers van de Rice-universiteit werken samen met verschillende bedrijven en hebben al een werkende prototype-geheugenchip met duizend elementen. Deze wordt nu getest.

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HP moves to revolutionize computing

HP has worked up quite a reputation for being the king of drama over the last several years. However, this week the company shifted the drama where it belongs: with the products.

Yes, HP announced an ARM based server platform targeted at Cloud applications that promises to significantly reduce server costs for companies like Amazon, Google, Facebook and other entities who live off of the web.

Genre classics resurrected as graphic novelsYet, this is just the beginning of a much bigger revolution.

In a session after the announcement, HP Labs talked about the new as the first step to replace processor architectures, networking, and storage as we know it with a fabric based on their unique Memristor technology which is apparently close to initial test fabrication.

This would suggest HP is actually on the cusp of a revolution similar to the transistor. If properly executed, the new paradigm could put the company at the heart of an intense technology storm.

The Problem with Current Architectures

Remember, whether we are talking PCs or servers, the base architecture goes back decades to before there was a web or high speed networks. Repositories were, back in the days of yore, measured in megabytes. Now they are gauged in terabytes, with bottlenecks moving from slow processors, to slow memory, latency and crawling networks. As such, most forms of storage and traditional copper networking has become increasingly inadequate and will likely hit a wall in a few short years.

Add these limitations to the cloud, the massive movement of data to the most optimized resource, and virtualization. What do you get? The potential for the mother of all performance killers - the current server and storage architecture.

Memristors + Tiny Cheap Cores

But what if you could break the storage, networking, and processor elements into tiny parts that could be reassigned and grouped in close proximity on demand?

Well, Memristors represent the best aspects of both magnetic media (they are non-volatile) and flash (they are fast to read and write, consume little power, and are solid state). So, what if you took these storage elements and put them in groups in close proximity, perhaps on the same boards, as ARM processors?

You’d then have ultrafast high-capacity storage in extreme proximity to power efficient cores. Meaning, half Memristor-powered racks would likely be equivalent to several racks of more traditional products. In addition, the close proximity, coupled with the high on-board speed and optical fiber connections between the boards, should result in not only a sharp performance increase but also facilitate massive power savings.

While the end products likely would initially look a lot like existing server blades or rack mounted servers, they could be built in almost any configuration; as while the circuit density is high, the thermal requirements are actually comparatively low. Since proximity will be the major problem - imagine servers that look more like balls or cubes than they do today at some future point to minimize the distance between components that may need to dynamically share loads.

In short, HP opened up a can of whoop-ass on the technology market and we really don’t see that very often.

Wrapping Up: Personal Technology?

Smartphones and tablets kicked off the trend toward very low cost cores and eventually, what appears to be an aggressively redesigned computing architecture. However, many of these changes can be applied to future generations of PCs, tablets and smartphones - providing ever higher performance at ever lower battery life.

Just try and think of future devices that will revolutionize the market by making current-gen iPads and iPhones look fat, slow, and power hungry. Of course, irrespective of whether or not this actually happens, the good news is that HP is back to providing product drama, something which is long overdue. The Meg Whitman HP is certainly looking better and better all the time.

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We report sub-nanosecond switching of a metal–oxide–metal memristor utilizing a broadband 20 GHz experimental setup developed to observe fast switching dynamics. Set and reset operations were successfully performed in the tantalum oxide memristor using pulses with durations of 105 and 120 ps, respectively. Reproducibility of the sub-nanosecond switching was also confirmed as the device switched over consecutive cycles.

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In this work we demonstrated a platform for conducting
broadband dynamical studies of impedance mismatched
memristors. Tantalum oxide junctions were fabricated on
coplanar waveguide structures and reproducible resistance
switching of the order of 100 ps was shown. The measured
switching speed of this nonvolatile memory element is
comparable to or faster than mainstream volatile memories
such as DRAM and SRAM, and four orders of magnitude
faster than mainstream nonvolatile Flash. Additionally, the
result presented here opens new possibilities for the use of
memristors in high-speed high-frequency circuit applications.

......

The observed switching speed in this experiment was
limited by the pulse generator and not by the memristive device
itself nor by the transmission line structure. As a consequence,
one can envision that faster switching speeds in the double
digit picosecond range might be obtained by employing a faster
pulse generator as well as a compatible sample area in order to
minimize the parasitic effects associated with the memristor’s
parasitic capacitance.

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During IDEM, which is held in Washington, D.C. this week, the European research institute IMEC has shown the first 10nm RRAM cell. RRAM is often also referred to as a memristor.

The area of the cell is 100nm² and is based on hafnium/hafnium-oxide as the switching material. This material is placed between conventional contacts in a cross bar array. The contacts are made of titanium-nitride.

Cross section of IMEC 10nm RRAM cell. Copyright IMEC.

The cell has demonstrated an endurance of more than 1 billion reads/writes and switches in about 1ns. IMEC has extrapolated the data retention period to 10 years at 100 degrees C. Excellent life-span next to a hot GPU.

If manufacturing hurdles can be overcome, then this cell clearly demonstrates that RRAM will be superior to both NAND flash as well as conventional DRAM.

In order to use its potential fully then programmers will start to think of different ways to write programs since memory and storage over time could merge to one large linear space.

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Elpida Announces 64Mb ReRAM, Sees 8Gb Product in 2013

Jan 26, 2012 12:03 Jyunichi Oshita, Nikkei Electronics

Elpida Memory had a press conference Jan 24, 2012, and Takao Adachi, who is responsible for the development of the new memory, explained about the latest technology.

The new ReRAM. Each of its four areas is a 64-Mbit memory array.

Elpida Memory Inc developed ReRAM (resistive random-access memory), which is expected to be one of the next-generation nonvolatile memories.

The company prototyped the ReRAM by using 50nm process technology to form 64-Mbit cell arrays and confirmed operation of all bits. It has already started making efforts towards commercialization of the ReRAM.

"We want to launch an 8-Gbit product made by using 30nm process technology (as the first product) in 2013," said Takao Adachi, director of Elpida. "We will be ready for full-scale volume production in 2014."

Elpida plans to target the ReRAM at mobile machines such as smartphones, tablet computers and notebook computers. It expects that the ReRAM will be used as cache memory to fill a performance gap between DRAM and NAND flash memory in those machines.

"We hope that it will eventually be a memory that can replace DRAM because mobile machine makers want to reduce the amount of DRAM (which consumes a large amount of power) as much as possible and replace it with nonvolatile memory," Adachi said.

At this point, however, many of its customers that develop video-related stationary machines and want to enhance the speed of SSD are showing interest in the ReRAM, he said.

The new ReRAM is a 1T-1R-type ReRAM developed by using variable resistance elements based on hafnium (Hf) oxide. Its data reading speed is 20ns or faster, and it can be rewritten one million times or more. Elpida plans to completely clarify the mechanism of its operation and reduce the variation in the operation of memory elements in the aim of increasing its capacity to higher than 1 Gbit.

Though the ReRAM was prototyped by using 6F2 cells this time, Elpida intends to use 4F2 cells for volume production of the memory and reduce cell area. It can be mass-produced in production lines for DRAMs. For volume production, the company aims to achieve a bit cost 30% lower than that of DRAM.

Elpida has already decided to develop only ReRAM as its next-generation nonvolatile memory and is not developing MRAM (magnetic random access memory) or PRAM (phase-change random access memory).

The ReRAM was developed in collaboration with Sharp Corp, Japan's National Institute of Advanced Industrial Science and Technology (AIST) and the University of Tokyo in a project sponsored by New Energy and Industrial Technology Development Organization (NEDO) (See related article). The project was launched in 2010.

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Panasonic and TSMC Tip Resistive RAMs at ISSCC
Foundry looking for embedded memory solution

-----------------------
By Mark LaPedus, SemiMD senior editor

The emerging resistive RAM (ReRAM) market continues to heat up, as Panasonic and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) will describe new breakthroughs in the arena.

At the International Solid-State Circuits Conference (ISSCC) in San Francisco on Wednesday (Feb. 22), TSMC will describe a ReRAM as part of the silicon foundry’s push in the embedded memory space. TSMC, along with National Tsing Hua University in Hsinchu, Taiwan, will disclose the development of a 0.5-Volt, 4-Mbit embedded ReRAM macro, based on a 65nm logic process.

At ISSCC, Panasonic will describe an 8-Mbit multi-layered cross-point ReRAM macro. The device has a 443-MB/second write throughput at 8.2nm pulse widths, which is twice as fast as competing efforts, according to Panasonic. Read access time is said to be 25ns.

Last year, Panasonic claimed to be sampling a 2-Mbit ReRAM, based on a tantalum and oxygen (TaOx) process. The 8-Mbit ReRAM uses the same technology, reportedly based on a 0.18-micron process.



Panasonic's ReRAM structure (Source: Company)

The ISSCC announcements follow what could be the hottest technology within the next-generation memory space. Elpida, Hynix, IMEC, Micron, Samsung, Sharp, Sony and others are working on ReRAM. ReRAM is “based on the electronic switching of a resistor element material between two stable (low/high) resistive states. The major strengths of ReRAM technology are its potential density and speed,” according to IMEC.

FRAM, MRAM, phase-change, ReRAM and others fall into the so-called universal memory category. Developers of these technologies claim their respective technologies can replace DRAM, NAND and NOR — or all three.

Most next-generation memory types have failed to live up to their promises. They are difficult to make and scale. But some claim the floating gate structure in flash is expected to hit the wall at 14nm, thereby fueling the need for a new memory type.

There are a range of emerging applications for next-generation memories. One of the possibilities is so-called storage-class memories. In this application, there is a need for a new and faster memory that sits between the processor and DRAM in a system to boost I/O performance. In theory, a storage-class memory would offload many of the functions in a power-hungry DRAM.

Block diagram of ReRAM from National Tsing Hua University and TSMC (Source: TSMC, National Tsing)
Embedded is another application. Many foundries offer embedded DRAM IP for system LSIs and other applications, but the technology could soon hit the scaling wall.

In embedded applications, “MRAM and ReRAM have the most promise,” said Fu-Lung Hsueh, a TSMC fellow and director of the Design Technology Division for the foundry giant, in a brief interview at ISSCC.

For some time, TSMC and Qualcomm Inc. have been developing an embedded memory based on MRAM technology. In the future, Qualcomm hopes to incorporate the MRAM IP within its cell-phone chip offerings.

ReRAM is another possibility for the embedded market. TSMC and National Tsing Hua University are developing a ReRAM solution. Hsueh said the device is still in the “prototyping” stage and the work is being conducted at the university level.
That device is said to enable short write times at low voltages. The 4-Mbit macro has four 1-Mbit sub-arrays, comprising of 2,048 columns and 512 rows, according to a paper from TSMC and National Tsing Hua. The entities developed a body-drain-driven current-mode sense amplifier (CSA) and small voltage headroom (VHR) for larger sensing margins. Using a new sensing scheme, the device is said to have a 45ns random read time, according to the paper.

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Ook Sandisk zet in op SSD-killer ReRAM
Geheugen van de toekomst
22 februari 2012 | Jan Custers
ZDNet.nl

Flashgeheugenfabrikant Sandisk zet een team van specialisten op de ontwikkeling van ReRAM-geheugen. Dat zou zowel het hedendaagse werk- als opslaggeheugen kunnen vervangen.

Sandisk plaatste vorige week een vacature op zijn website voor een verantwoordelijke van een dertigkoppig onderzoeksteam dat de productie van op memristors gebaseerd resistief RAM-geheugen (ReRAM) mogelijk moet maken. Het doet dat in samenwerking met partner Toshiba. Dat merkte Bright Side of News op.

Technologie evolueert snel
Vorige maand beweerde de Japanse geheugenfabrikant Elpida dat het samen met elektronicagigant Sharp een prototype van ReRAM-geheugen had ontwikkeld met dezelfde lees- en schrijfsnelheden als het DRAM-geheugen in hedendaagse computers.

Ook Panasonic, Sony, Micron, DSI en HP - in samenwerking met Hynix Seminconductor – investeren in de technologie. Die steunt op de revolutionaire ‘memristor’ die HP in 2008 ontwikkelde. Het eerste commerciële ReRAM-product wordt rond 2013 verwacht.

Snel en niet-vluchtig
ReRAM wordt naar voren geschoven als de opvolger van zowel het huidige systeem- als opslaggeheugen in computers. De technologie combineert de lees- en schrijfsnelheid van DRAM-geheugen met de niet-vluchtige aard van flashgeheugen. Dat betekent dat gegevens bewaard blijven als de spanning wegvalt. In theorie zal een computer met genoeg ReRAM-geheugen geen laadtijden meer kennen.

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Samsung realizes ReRAM's rewritability of one trillion times


Resistive Random Access Memory (ReRAM) technology has been making the news rounds throughout the electronic market since its inception back in 1997. Panasonic had led the way for commercial mass production as this next generation iteration of non-volatile memory types is being developed by a multitude of companies. But this time, Samsung has rather notched a level by contriving a performance enhancing technology, which boosts the ReRAM's rewritability capacity to a mind-boggling 1 trillion times!



Fundamentally, this new advanced technology utilizes asymmetric Ta2O5-x/TaO2-x bi-layer laminated film as the resistivity-varying material, instead of the conventional Ta2O5 film. The new material contributes to localized resistance switching. The reduction in switching current in turn allows for lesser power consumption, along with extreme cycling endurance of over 1 trillion.

The figures speak for themselves as this touted one trillion mark capability is about one million times more than that of the latest flash memory. Moreover, with switching times of only 10ns, the fascinating technology can be applied in cases of working-memory space.

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IMEC to detail memristor progress at VLSI Symposia
R. Colin Johnson

PORTLAND, Ore.— The Interuniversity Microelectronics Centre (IMEC) will report next month on progress to make its memristor variation, called resistive-RAMs (RRAM), the dominate memory technology in four papers at the VLSI Symposia in Honolulu.

At the Symposia June 12 to 15, IMEC (Leuven, Belgium), which claims RRAM will be ready for reliable mass production below 20 nanometers, will describe its cross-bar architecture. IMEC claims the architecture is denser, faster and lower-power than flash, but suitable to replace any memory type, including DRAMs.

IMEC and other research groups backing variations of the memristor claim that, in the future, a single universal memory technology will replace flash memory and all vintages of random-access memories. The memristor was invented by by professor Leon Chua at the University of California-Berkeley and has been championed by Hewlett-Packard Co.

"HP is using the term memristor to describe a device which has certain I-V characteristics," said Malgorzata Jurczak, program manager memory devices at IMEC. "But such I-V characteristics are typical to any RRAM cell using oxygen vacancy migration in transition metal oxide."

HP is sandwiching titanium-oxides in its memristive crossbar arrays, but at VLSI Symposia IMEC will describe using hafnium-oxide and other formulations for its RRAMs. In addition, there are two different ways of performing the resistive switching, using interfacial modification where oxygen vacancies are migrated either towards or away from the interface, thus modulating the tunneling barrier between the electrode and the conductive part of the oxide. Alternatively, filamentary switching aligns the oxygen vacancies in a conduction path which can be ruptured or established by oxygen vacancy migration. Either way, the advantage is the same—ultra-high density cross-bar arrays that use programming voltages to migrate oxygen vacancies, thereby changing the resistance of the bit-cell in a non-volatile manner.

"HP is claiming to using interfacial type of switching," said Jurczak. "But in our papers we are using filamentary switching."

IMEC will report that it has achieved ultra-fast sub-nanosecond programming times and ultra-low power sub-500 nanoamp operating currents using filamentary switching. IMEC will also report improved bit-cell reliability by virtue of its sophisticated materials stack engineering.

"We are overcoming the scaling limitations of conventional flash memory cells," said Jurczak. "Major memory players joined our research program on emerging memory technologies, proving the value of our RRAM research to the global industry."

Summary titles of IMEC's four papers are: "Dynamic ‘Hour Glass’ Model for Set and Reset in Hafnium Oxide RRAM," "Ultralow sub-500nA Operating Current in High-Performance Bipolar RRAM Achieved Through Understanding-Based Stack-Engineering," "Process-Improved RRAM Cell Performance and Reliability and Paving the Way for Manufacturability and Scalability for High Density Memory Application," and "Field-Driven Ultrafast sub-ns RRAM Programming."

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Intel bouwt chip die hersenen nabootst

Door Bauke Schievink, maandag 18 juni 2012

Intel heeft een chip gemaakt die op vergelijkbare wijze werkt als het neurale netwerk in de hersenen. Zo zorgen de componenten in de chip er onder meer voor dat een elektrisch signaal net als bij neuronen via pulsen worden doorgestuurd.

De technologie is gebaseerd op lateral spin valves en memristors. De eerstgenoemde zijn kleine magneetjes die hun magnetisch veld van richting kunnen laten veranderen op basis van de spin van elektronen. Tezamen met memristors, weerstanden met geheugen, levert dit een circuit op waarin de elektrische signalen niet met een constante spanning worden doorgestuurd, maar juist pulserend werken.

Volgens de onderzoekers, die werkzaam zijn bij Intel, werken de spin valves in de chip op een aanzienlijk lagere spanning dan conventionele chips. De benodigde spanning is volgens de makers uit te drukken in millivolts, net als de neuronen in de hersenen. Uiteindelijk moet een dergelijk systeem, dat een neuromorphic chip wordt genoemd, het stroomverbruik kunnen terugdringen met een factor 15 tot 300 ten opzichte van conventionele chips.

In de hersenen worden ook elektrische circuits gevormd, waarvan neuronen de basis zijn. Zij vormen een elektrisch systeem waarin zij na activiatie signalen in pulsvorm doorsturen. Daarbij wordt een sterker signaal weergegeven door een hogere frequentie van elektrische prikkels. Uiteindelijk worden de signalen geïntegreerd in het centrale zenuwstelsel, waarvan het brein het hoofdbestanddeel is.

De door Intel ontworpen chip kan ingezet worden om rekenkernen mee te maken die op vergelijkbare wijze werken als de hersenen, waardoor simulatie gemakkelijker wordt. Dergelijke systemen kunnen worden ingezet om de hersenen te bestuderen, maar ook om meer rekenkracht mogelijk te maken bij een lager stroomverbruik. Wel is daarvoor meer onderzoek nodig. Hoewel een neuromorphic chip al voor hersenachtige systemen kan worden ingezet, is er meer nodig om daarvan een volledig functionerend systeem te maken.

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Op maandag 18 juni 2012 15:55 schreef Ai_KaRaMBa het volgende:

[..]

Uhm, nee? Transistor en diode zijn wel fundamentele elementen. Het onderscheid zit hier tussen passieve lineare componenten en actieve non-lineare componenten (halfgeleiders). Een memristor is geen passief linear component, en zal dus ook niet in dat rijtje passen.

Verder is een natuurkundige eenheid van memristor ook kolder als ik je verhaal goed begrijp, want je kan dmv een instelstroom (ampere) boven drempelspanning (volt) de weerstand (ohm) onder de drempelspanning instellen. Dat is dus prima uit te drukken als een verband tussen de andere grootheden, en daar hoeft dus geen nieuwe grootheid voor bedacht te worden lijkt me...

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Op maandag 18 juni 2012 18:20 schreef Ai_KaRaMBa het volgende:
Ik bedoelde component idd; maar feit blijft dat die menristor ook een halfgeleider is, net als de transistor en diode. toch?

edit: artikel bekeken, en daar noemen ze het ook "basic element"... dubieus ?!

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Aren't there other fundamental passive devices that don't add energy to a circuit? What about diodes?


No, there are only four fundamental types of passive circuit elements. Diodes are just non-linear resistors - the resistance of a diode changes with the applied voltage, but if you turn off the voltage and start back at 0 volts, the resistance of the diode is the same as it was before at 0 volts, not what it was when the voltage was turned off. This is also true of a resistor that heats up and increases its resistance because of a temperature increase. Thus, neither a diode nor a heated resistor 'remember' their history. However, each type of fundamental circuit element is actually a family of devices with essentially an infinite number of higher order members. To see all the members of the four families of fundamental devices, see the following paper: Leon O. Chua, "Nonlinear Circuit Foundations for Nanodevices, Part I: The Four-Element Torus," Proc. IEEE 91, 1830-1859 (2003). This is a very educational paper, but requires a significant investment in effort to appreciate. Note: Part II has not appeared in the literature yet.

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Pc's met nieuw geheugenelement memristor pas in 2014
AMSTERDAM - HP-computers met de memristor, een nieuw geheugenelement waardoor chips onder meer energiezuiniger en goedkoper moeten worden, zijn vertraagd tot begin 2014.

Foto: HP Dat laat het hoofd van de onderzoeksafdeling van HP weten.

In eerste instantie zouden de producten met memristors, een afkorting voor memory resistor, al in 2013 beschikbaar zijn.

De grootste pc-fabrikant wereldwijd maakte de ontdekking van het nieuwe elektronische component in 2008 al bekend en omschrijft het als 'het godselement in de elektronica'.

Geheugen

De memristor zou de opvolger van de transistor moeten worden. Door het nieuwe geheugenelement moeten processors veel energiezuiniger worden en zal het productieproces van chips goedkoper moeten zijn.

Op termijn zou de memristor zelfs het opslaan van gegevens op het werkgeheugen fundamenteel kunnen veranderen. Het component kan het werkgeheugen en vaste opslag namelijk combineren. Nu is dat nog gescheiden en worden gegevens op verschillende plekken opgeslagen.

Vervangen

De memristor kan alle gegevens op één plek opslaan en zo flashgeheuden, SSD, en RAM-geheugen vervangen. Dat levert ruimtebesparing in computers op. Ook is het geheugen dan niet meer gevoelig voor stroomuitval.

Niet alleen computers zullen profiteren van de nieuwe technologie, alle elektronische apparaten kunnen gebruikmaken van memristors.

2014

Apparaten met de nieuwe techniek komen waarschijnlijk pas in 2014 uit omdat er grote economische belangen aan de lancering verbonden zijn. Zo moet Hynix, de partner van HP bij het produceren van memristors, een flinke verandering ondergaan. Nu produceert het bedrijf bijvoorbeeld nog flashgeheugen.

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Micron brengt phase change-geheugen voor mobiele apparaten uit

Micron heeft de eerste chips met phase change-geheugen voor grootschalige afname beschikbaar gemaakt. De geheugenfabrikant gaat producten leveren waarin een phase change-geheugen met een 1Gb-chip zit, gecombineerd met 512Mb ddr2.

De nieuwe geheugenchips, of correcter: packages met de pcm-chips en lpddr2-chips erin, zullen aan fabrikanten van mobiele apparatuur als laptops, tablets en mobiele telefoons geleverd worden. De packages zouden vooral geoptimaliseerd zijn voor zogeheten feature phones, later zouden geavanceerdere toestellen als smartphones en tablets volgen. Volgens Micron biedt de beschikbaarheid van de packages fabrikanten van chipsets en mobieltjes de gelegenheid hun producten te optimaliseren om van de voordelen van phase change-geheugen te profiteren.

Phase change-geheugen zou een stuk zuiniger zijn dan conventioneel geheugen en bovendien een langere levensduur hebben. Apparaten zouden onder meer sneller starten met Microns pcm-chips aan boord. Het phase change-geheugen dat door Micron ontwikkeld werd, wordt op 45nm geproduceerd. Het werkt niet zoals conventioneel geheugen door lading in condensators vast te houden en zo bits op te slaan. In pcm is het verschil in weerstand tussen een kristallijne vorm en een amorfe toestand van een speciaal materiaal verantwoordelijk voor de enen en nullen. Het geheugentype ontleent zijn naam aan de overgang tussen de twee toestanden, de phase change.

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Synaptic electronic circuits that learn and forget like neural processes

mana_synaptic_electronics

(a): Volatile (short-term) memory property of two terminal device before the forming process. Current change observed by applying sequence of positive voltage pulses at intervals of 40 s and widths of 0.5 s. (b): Nonvolatile (long-term) memory property in the device after the forming process following application of a sequence of positive and negative pulses with widths of 0.1 ms. (c): Schematic illustration of the device structures before and after forming process. (Credit: MANA, NIMS)

Rui Yang, Kazuya Terabe and colleagues at the National Institute for Materials Science (NIMS), and the International Center for Materials Nanoarchitectonics (MANA) in Japan and at the California NanoSystems Institute/UCLA have developed “nanoionic” (processes connected with fast ion transport in all-solid-state nanoscale systems) devices capable of a broad range of neuromorphic and electrical functions.

Background

Such a device would allow for fabrication of on-demand configurable circuits, analog memories, and digital-neural fused networks in a single device architecture.

Synaptic devices that mimic the learning and memory processes in living organisms are attracting interest as an alternative to standard computing elements to help extend performance beyond current physical limits. However, artificial synaptic systems have been hampered by complex fabrication requirements and limitations in the learning and memory functions they mimic.

How it works

The device is based on a platinum-tungsten trioxide (WO3–x) device using oxygen ions migrating in response to voltage sweeps. Accumulation of the oxygen ions at the electrode leads to Schottky diode-like potential barriers and resulting changes in resistance and rectifying characteristics. The stable bipolar switching behavior at the platinum-tungsten trioxide-based device is attributed to the formation of a conductive filament and oxygen absorbability of the platinum electrode.

The researchers noted that the device properties* — volatile and non-volatile states and current fading following positive voltage pulses — are similar to neural behavior — that is, short- and long-term memory and forgetting processes.

The device was found to possess a wide range of time scales of memorization, resistance switching, and rectification varying from volatile to permanent in a single device.

“These capabilities open a new avenue for circuits, analog memories, and artificially fused digital neural networks using on-demand programming by input pulse polarity, magnitude, and repetition history,” the researchers conclude.

* In its initial pristine condition the system has very high resistance values. Sweeping both negative and positive voltages across the system decreases this resistance nonlinearly, but it soon returns to its original state, indicating a volatile state. Applying either positive or negative pulses at the top electrode introduces a soft breakdown, after which sweeping both negative and positive voltages leads to non-volatile states that exhibit bipolar resistance and rectification for longer periods of time.

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The neuristor HP-labs

The Hodgkin–Huxley model for action potential generation in biological axons1 is central for understanding the computational capability of the nervous system and emulating its functionality. Owing to the historical success of silicon complementary metal-oxide-semiconductors, spike-based computing is primarily confined to software simulations2, 3, 4 and specialized analogue metal–oxide–semiconductor field-effect transistor circuits5, 6, 7, 8. However, there is interest in constructing physical systems that emulate biological functionality more directly, with the goal of improving efficiency and scale. The neuristor9 was proposed as an electronic device with properties similar to the Hodgkin–Huxley axon, but previous implementations were not scalable10, 11, 12, 13. Here we demonstrate a neuristor built using two nanoscale Mott memristors, dynamical devices that exhibit transient memory and negative differential resistance arising from an insulating-to-conducting phase transition driven by Joule heating. This neuristor exhibits the important neural functions of all-or-nothing spiking with signal gain and diverse periodic spiking, using materials and structures that are amenable to extremely high-density integration with or without silicon transistors.

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Op donderdag 27 december 2012 16:42 schreef Senor__Chang het volgende:
tl;dr?

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Onderzoeker wil memristors gebruiken voor neurale netwerken

Een Duitse onderzoeker wil een kunstmatig brein bouwen met memristors als belangrijkste bouwstenen. Dergelijke neurale netwerken zouden tot leren in staat moeten zijn. De wetenschapper wil een blauwdruk voor de bouw van kunstmatige hersenen ontwikkelen.

De Duitse onderzoeker Andy Thomas is docent aan de natuurkundefaculteit van de universiteit van Bielefield en publiceert zijn plannen voor een blauwdruk in maart in het Journal of Physics. Uitgangspunt voor de bouw van een neuraal netwerk dat tot leren in staat is, moet het gebruik van memristors zijn. Die relatief recent ontdekte elektronische bouwstenen zijn passieve elementen, net als weerstanden. Anders dan weerstanden behoudt een memristor echter zijn laatste weerstand wanneer het circuit onderbroken wordt. Aan dat geheugengedrag dankt de memristor zijn naam.

Bovendien zou een 'geheugenweerstand' die zijn laatste weerstand onthoudt, het elektronische equivalent van een synaps zijn. In hersenen zorgen synapsen voor de onderlinge verbindingen tussen neuronen. Omdat memristors in functie op synapsen lijken, wil Thomas ze inzetten als bouwstenen voor zelflerende neurale netwerken. Hun geschiktheid werd al eerder aangetoond door Thomas' eigen onderzoeksgroep en door andere onderzoekers, onder meer van Intel.

Omdat de weerstand van een memristor afhankelijk is van de stroom die er doorheen gaat, is veel meer variatie mogelijk dan bij bits; die kunnen immers alleen een 1 of een 0 representeren. Memristors fungeren meer analoog, zoals samenwerkende synapsen in hersenen dat ook doen. Bovendien zou een neuraal netwerk met memristors niet alleen in staat zijn tot leren, maar ook tot vergeten. Een dergelijk neuraal netwerk is in theorie ook te bouwen met conventionele, op transistors gebaseerde circuits, maar gebruik van passieve componenten als memristors, met hun aan synapsen analoge functie, maakt dat een stuk eenvoudiger.

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Resistive RAM – A New Approach

Resistive random-access memory (RRAM) is widely hailed as the “most likely to succeed” in the race to develop a new more scalable, high capacity, high performance and reliable memory.

Typical RRAM cells are based on a switching material with different resistance characteristics sandwiched by two metallic electrodes. The switching effect of RRAM is based on the motion of ions under the influence of an electric field or heat, and the ability of the switching material to store the ion distribution, which in turn causes a measurable change of the device resistance.

Compared to traditional Flash memory, RRAM is faster, bit-alterable and requires lower voltage, enabling its use in both embedded and SSD applications. The simple RRAM cell structure offers best area efficiency (4F2 cell) and excellent scalability and 3D integration potential (both 3D stacking and vertical cell). RRAM requires lower programming currents than PCM or MRAM with comparable performance in terms of retention and endurance.

There are different approaches to implementing RRAM, based on different switching materials and memory cell organization. Those variables drive significant performance among the different materials being used.

RRAM has already been the subject of intense research and development, with several companies claiming to have prototype memory chips available in the next 1-2 years.

One of the biggest challenges for RRAM technology has been the integration of the RRAM array with standard CMOS technology and standard manufacturing processes. Crossbar RRAM technology has proven the manufacturability with a working array produced in a commercial fab. This working silicon is a fully integrated monolithic CMOS controller and memory array chip. The company is currently completing the characterization and optimization of this device and plans to bring its first product to market in the embedded SOC market.

Crossbar Technology - Real time TEM visualization of filament formation

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ARM investeert in ceram-geheugentechnologie

Door Dimitri Reijerman

ARM heeft geld gestoken in Symetrix, een bedrijf dat onderzoek doet naar correlated-electron ram, een relatief nieuw type niet-vluchtig geheugen. Ceram zou verder verkleind kunnen worden dan de huidige soorten flashgeheugen.

CeramCeram kan volgens Symetrix een goede opvolger zijn van de huidige nand-flashgeheugentechnologie die niet verder verkleind zou kunnen worden dan tot een 20nm-procedé. De Ceram-technologie, een verbeterd ontwerp ten opzichte van het moeilijk te fabriceren reram, zou schaalbaar zijn tot 5nm, zo stellen de makers. Ook zou de ceram-geheugentechnologie in socs geïntegreerd kunnen worden.

ARM heeft interesse in de ceram-technologie en heeft volgens de website Electronics360 besloten om geld te investeren in Symetrix. Onduidelijk is nog hoe hoog het bedrag is, maar ARM zou belangstelling hebben om de technologie op termijn mogelijk in licentie te nemen.

Tot nu toe heeft ARM zich vooral gericht op processortechnologie. Het bedrijf geeft zijn chipontwerpen in licentie uit aan fabrikanten. ARM-chips zijn vooral populair in mobieltjes en tablets dankzij het relatief geringe stroomverbruik.

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Non-Filamentary ReRAM

Carlos Paz de Araujo, a professor at the University of Colorado and an expert in ferroelectric memory and materials, has revealed that his company Symetrix Corp. is preparing to launch a non-filamentary, non-volatile memory technology based on the metal-insulator Mott transition in nickel oxide.

The development was revealed on the web pages of EE Times in an online forum discussing non-volatile memory in which Professor Araujo said he was "sick and tired of these electrochemical approaches claiming to solve all problems when in fact the beauty of metal-insulator physics is not utilized."

There have been numerous R&D initiatives to try and develop a resistive RAM (ReRAM) replacement for flash memory, but most of these are based on the making and breaking of conductive filaments within an insulating sandwich between electrodes. Understanding and controlling the physical processes behind the forming, maintenance, and breaking of such filaments, which can be just one or a few atoms in diameter, has proved difficult.

Professor Araujo claimed his approach is different in that it is non-filamentary and does not depend on mass transport. Instead it uses a metal-insulator transition that occurs throughout the metal-oxide crystal structure and that is dependent on electron correlation. The metal-insulator transition is controlled by doping, with nickel carbonyl as the dopant, Professor Araujo said in his comments.

"We call our device CeRAM -- Correlated Electron RAM -- to separate ourselves from the filament crowd," Professor Araujo wrote on the EE Times website.

"We are introducing this technology in two months. It is fully compatible with lithography down to 20nm and can go lower. It is free of complicated contact materials such as platinum. It uses aluminum, cobalt silicide and nickel silicide. Anneals at 400 degrees C and is integratable in 3D using the same electrodes with an already proven diode. The storage temperature is 400 degrees C and the read/write is in the picoseconds. Blue Sky? Not really, it is common sense to try to dope nickel oxide instead of breaking it with filaments," Professor Araujo wrote.

Professor Araujo added that the technology reads at 0.2 volts, writes at 0.6 and 1.2 volts, and has a read endurance above 10^13 cycles, which is far in excess of the numbers quoted for flash memory at the leading-edge and for most alternative ReRAM technologies.

The end of scaling for the mainstream non-volatile memory technology, flash memory, which is based on electron storage, has been predicted for many years. Flash memory has just started to be implemented in multiple layers at relaxed minimum geometries to try and circumvent this issue. (See Samsung Confirms 24 Layers in 3D NAND.)

ReRAM memory, often based on layered metal-oxide materials, including transition metals, has yet to enter high-volume production and phase-change memory (PCM) although commercially deployed is only made at a lower storage density and features sizes much larger than flash memory.

Symetrix, based in Colorado Springs, Colo., was formed in 1986 by Professor Araujo to work on ferroelectric materials for use in non-volatile memory. Symetrix advocated the use of strontium barium titanate (SBT) as an alternative perovskite to lead zirconate titanate (PZT) for use in non-volatile ferroelectric random access memories (FeRAMs). Symetrix, which operates an IP-licensing business model, has licensed its technology to a number of semiconductor companies.

"We do not follow the capital-raising path and we are 27 years old with a portfolio of over 200 patents. We sold many licenses, and the royalty stream is enough to continue innovation," Professor Araujo wrote, but added that the company might be open to equity investment to accelerate the development of CeRAM.

EE Times wrote to Professor Araujo with supplementary questions about the nickel-oxide memory technology, but he declined to provide further information for publication at this time.

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HP claimt smartphones met 100 terabyte opslag

HP heeft een nieuwe computerarchitectuur gepresenteerd die zuiniger en zes keer sneller is dan de huidige servers en in staat is smartphones 100 terabyte opslagruimte te geven.
HP claimt smartphones met 100 terabyte opslag.

HP heeft zijn nieuwe architectuur de naam The Machine gegeven, en noemt het een van de grootste doorbraken op computergebied in decennia.

In eerste instantie is de nieuwe computerarchitectuur ontworpen om beter om te kunnen gaan met de grote datastroom van het zogenoemde Internet of Things. Dat is een verzamelnaam voor het groeiend aantal huishoudelijke en consumentenapparaten met (zelfstandige) internettoegang.

Zo heeft The Machine niet enkele krachtige processorkernen, maar clusters van vele kleinere processoren die specifieke taken uitvoeren. Alles is verbonden met fotonica: optische gegevensoverdracht die veel sneller moet zijn dan de huidige koperen kabels. Ionen worden daarbij in plaats van elektronen gebruikt voor het maken van berekeningen.

Razendsnel geheugen

Ook bevat The Machine zogenoemde memristors; de opvolger van de transistor die niet alleen gebruikt kan worden voor rekentaken, maar ook voor opslag. Dat maakt dat het permanente geheugen van The Machine zo snel is als werkgeheugen. Door die twee stappen in het computerproces te combineren, zijn bovendien kleinere, zuinigere apparaten met meer opslagruimte mogelijk.

The Machine kan volgens HP 160 petabyte (160 miljoen gigabyte) aan data in 250 nanoseconden behandelen. Dat is zes keer sneller dan huidige serverhardware, toch verbruikt The Machine daarbij 80 procent minder energie.

Geen koper

Omdat de architectuur van The Machine geen koper gebruikt, maar fotonica, zijn andere vormen van computers mogelijk. Daarom denkt HP dat het de technologie ook kan laten krimpen voor gebruik in laptops en smartphones.

"Vandaag de dag wisselen al onze apparaten, van telefoon tot supercomputer, constant informatie uit tussen drie lagen van geheugen", legt HP uit. "We hebben het SRAM voor informatie die nu nodig is, het DRAM voor informatie die spoedig nodig is, en het opslaggeugen voor data die later nodig is. Memristors zullen een snelle, goedkope manier zijn die DRAM en opslag combineert. Door het elimineren van een stap maken we processen sneller en zuiniger. Denk aan 100 terabyte opslag in je mobiele telefoon."

Het gaat dan met name om die memristors, die meer en snellere opslag in een kleinere verpakking mogelijk maken. Dit geheugen is pas volgend jaar in testhoeveelheden verkrijgbaar. De eerste apparaten die gebruik maken van de techniek van The Machine worden in 2018 verwacht.

Toch benadrukt HP dat The Machine nog een onderzoeksproject is, wat het onduidelijk maakt of en wanneer de technologie daadwerkelijk te gebruiken is

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Use of porous silicon oxide reduces forming voltage, improves manufacturability

HOUSTON — (July 10, 2014) — Rice University’s breakthrough silicon oxide technology for high-density, next-generation computer memory is one step closer to mass production, thanks to a refinement that will allow manufacturers to fabricate devices at room temperature with conventional production methods.

This scanning electron microscope image and schematic show the design and composition of new RRAM memory devices based on porous silicon oxide that were created at Rice University. Credit: Tour Group/Rice University

First discovered five years ago, Rice’s silicon oxide memories are a type of two-terminal, “resistive random-access memory” (RRAM) technology. In a new paper available online in the American Chemical Society journal Nano Letters, a Rice team led by chemist James Tour compared its RRAM technology to more than a dozen competing versions.

“This memory is superior to all other two-terminal unipolar resistive memories by almost every metric,” Tour said. “And because our devices use silicon oxide — the most studied material on Earth — the underlying physics are both well-understood and easy to implement in existing fabrication facilities.” Tour is Rice’s T.T. and W.F. Chao Chair in Chemistry and professor of mechanical engineering and nanoengineering and of computer science.

Tour and colleagues began work on their breakthrough RRAM technology more than five years ago. The basic concept behind resistive memory devices is the insertion of a dielectric material — one that won’t normally conduct electricity — between two wires. When a sufficiently high voltage is applied across the wires, a narrow conduction path can be formed through the dielectric material.

This illustration depicts the rewriteable crystalline filament pathway in Rice University's porous silicon oxide RRAM memory devices. Credit: Tour Group/Rice University

The presence or absence of these conduction pathways can be used to represent the binary 1s and 0s of digital data. Research with a number of dielectric materials over the past decade has shown that such conduction pathways can be formed, broken and reformed thousands of times, which means RRAM can be used as the basis of rewritable random-access memory.

RRAM is under development worldwide and expected to supplant flash memory technology in the marketplace within a few years because it is faster than flash and can pack far more information into less space. For example, manufacturers have announced plans for RRAM prototype chips that will be capable of storing about one terabyte of data on a device the size of a postage stamp — more than 50 times the data density of current flash memory technology.

The key ingredient of Rice’s RRAM is its dielectric component, silicon oxide. Silicon is the most abundant element on Earth and the basic ingredient in conventional microchips. Microelectronics fabrication technologies based on silicon are widespread and easily understood, but until the 2010 discovery of conductive filament pathways in silicon oxide in Tour’s lab, the material wasn’t considered an option for RRAM.

Since then, Tour’s team has raced to further develop its RRAM and even used it for exotic new devices like transparent flexible memory chips. At the same time, the researchers also conducted countless tests to compare the performance of silicon oxide memories with competing dielectric RRAM technologies.

Rice University postdoctoral researcher Gunuk Wang, left, and chemist James Tour have demonstrated new techniques for using porous silicon oxide to make robust RRAM memory chips that can be easily manufactured with existing fabrication techniques. Credit: Jeff Fitlow/Rice University

“Our technology is the only one that satisfies every market requirement, both from a production and a performance standpoint, for nonvolatile memory,” Tour said. “It can be manufactured at room temperature, has an extremely low forming voltage, high on-off ratio, low power consumption, nine-bit capacity per cell, exceptional switching speeds and excellent cycling endurance.”

In the latest study, a team headed by lead author and Rice postdoctoral researcher Gunuk Wang showed that using a porous version of silicon oxide could dramatically improve Rice’s RRAM in several ways. First, the porous material reduced the forming voltage — the power needed to form conduction pathways — to less than two volts, a 13-fold improvement over the team’s previous best and a number that stacks up against competing RRAM technologies. In addition, the porous silicon oxide also allowed Tour’s team to eliminate the need for a “device edge structure.”

“That means we can take a sheet of porous silicon oxide and just drop down electrodes without having to fabricate edges,” Tour said. “When we made our initial announcement about silicon oxide in 2010, one of the first questions I got from industry was whether we could do this without fabricating edges. At the time we could not, but the change to porous silicon oxide finally allows us to do that.”

This electron microscope image shows the surface of the nanoporous silicon-oxide material used in Rice University's new RRAM memory devices. The red areas highlight gaps, or voids, in the material's amorphous silicon-oxide coating. Credit: Tour Group/Rice University

Wang said, “We also demonstrated that the porous silicon oxide material increased the endurance cycles more than 100 times as compared with previous nonporous silicon oxide memories. Finally, the porous silicon oxide material has a capacity of up to nine bits per cell that is highest number among oxide-based memories, and the multiple capacity is unaffected by high temperatures.”

Tour said the latest developments with porous silicon oxide — reduced forming voltage, elimination of need for edge fabrication, excellent endurance cycling and multi-bit capacity — are extremely appealing to memory companies.

“This is a major accomplishment, and we’ve already been approached by companies interested in licensing this new technology,” he said.

Study co-authors — all from Rice — include postdoctoral researcher Yang Yang; research scientist Jae-Hwang Lee; graduate students Vera Abramova, Huilong Fei and Gedeng Ruan; and Edwin Thomas, the William and Stephanie Sick Dean of Rice’s George R. Brown School of Engineering, professor in mechanical engineering and materials science and in chemical and biomolecular engineering.

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Resistive RAM nears launch: Still the most likely candidate to replace NAND flash

December 22, 2014

It’s been a while since we checked in on Crossbar, the next-generation memory company working on a NAND flash replacement. The company’s resistive RAM (RRAM or ReRAM) technology stores data by creating resistance in a circuit rather than trapping electrons within a cell. Now, the company has announced that it’s moving towards commercializing its designs. That means it’s proven that it can build hardware at existing foundries and can seek vendors to bring solutions to market.

There are several intrinsic advantages to ReRAM as compared to NAND flash. NAND has limited endurance, its lifespan degrades as process nodes shrink and cells become smaller, and the amount of error-correction required at each new node is steadily increasing. Performance gains have slowed since clocking NAND faster also tends to cause it to degrade, and the bulk of improvements are now delivered by improving either the NAND controller or the system interface — not the underlying performance of the NAND itself.

ReRAM solves many of these problems. Unlike NAND, it doesn’t need to be erased before its programmed, and it’s much faster than NAND by multiple metrics. It also consumes less power — Crossbar claims that NAND requires 1360 picojoules per cell to program, while RRAM cuts this to just 64 picojoules per cell. Programming power is just one aspect to overall SSD power consumption, but the company also claims that its technology supports storing two bits of data per cell (analogous to MLC NAND) and can be stacked into 3D

The company also claims that its technology can be used to reduce the complexity of the microcontroller itself — a significant potential advantage as this is one area where complexity and cost have been increasing as the task of flash management becomes more complicated.

Commercialization of consumer hardware, however, remains some time away. Crossbar has demonstrated that its designs can scale up into the terascale, but that doesn’t mean it’s ready to bring products at that density to market.

The firm is now licensing to ASIC, FPGA, and SoC developers, with samples arriving in 2015. Early expected target applications are the embedded and low-level applications shown in the chart above, where very little storage is required and low-power operation is essential.

One thing that hasn’t changed is the long-term roadmap for actual NAND flash replacement. Here’s where the realities of economic scaling come home to roost. Samsung, Intel, Micron — these companies have invested tens of billions of dollars into NAND production, and they aren’t going to shift to a new standard on a dime. For all that the tech industry likes to pride itself on rapidly adopting the latest and greatest technology, the truth is far different — the most successful products in computing are those that extend previous work in a cost-effective manner. Come-from-behind overtake maneuvers are actually quite rare, which is one reason why storage mediums tend to live for decades even when faster solutions are available in the market.

Right now, 3D NAND flash (Samsung calls it V-NAND) will drive the market from at least 2015 to 2018. That doesn’t mean we won’t see RRAM in consumer or enterprise applications — the market has snapped up more-expensive NAND flash solutions that leverage standards like PCI Express or the upcoming NVMe, particularly when these products can enable faster response times for high-frequency stock trading or other latency-critical applications. RRAM may not “feel” much faster than NAND, but it has the potential to provide better response times at latencies that matter to computers, and that’s enough of a reason for certain segments to adopt the equipment.

Earlier this year, we covered advances in other NAND flash replacements, such as phase change memory (PCM). These designs have demonstrated substantially improved performance compared to NAND, but also face significant scaling challenges and cost concerns. RRAM uses conventional CMOS hardware and can operate at scales down to 5nm. NAND flash, in contrast, isn’t expected to scale below 10nm on even the most optimistic roadmaps, and it’s not certain it will even get that low.

3D NAND will extend this further by allowing companies to step back up to higher nodes (Samsung’s current V-NAND is built on 40nm process technology). It’s not necessarily fair to call that a stopgap when it could slap 5-10 years on NAND scaling, but it’s still a long-term functional limitation. We’re going to need to replace flash with some alternate form of memory in the long term if we want to continue to improve power consumption and scale compute capability upwards, and right now RRAM looks like the most practical near-term option.

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3D Xpoint memory: Faster-than-flash storage unveiled

A new kind of memory technology is going into production, which is up to 1,000 times faster than the Nand flash storage used in memory cards and computers' solid state drives (SSDs).

The innovation is called 3D XPoint, and is the invention of Intel and Micron.

The two US companies predict a wide range of benefits, from speeding up scientific research to making more elaborate video games.

One expert described it as a "huge step forward".

"There are other companies who have talked about new types of memory technology, but this is about being able to manufacture the stuff - that's why they are making such a big deal out of it," says Bob O'Donnell, from the consultancy Technalysis.
If all goes to plan, the first products to feature 3D XPoint (pronounced cross-point) will go on sale next year. Its price has yet to be announced.

Intel is marketing it as the first new class of "mainstream memory" since 1989.

Rather than pitch it as a replacement for either flash storage or RAM (random access memory), the company suggests it will be used alongside them to hold certain data "closer" to a processor so that it can be accessed more quickly than before.
So, what's the big advantage over flash memory?

3D XPoint does away with the need to use the transistors at the heart of Nand chips.

Nand works by moving electrons back and forth to an isolated part of the transistors known as their "floating gates" to represent the ones and zeros of binary code.

An issue with this technique is that it cannot rewrite single bits of data at a time. Instead, larger blocks of information have to be wiped and then rewritten to incorporate the changes.

"It's kind of like a parking lot where you want to move one of the cars, but they are all jammed in," Intel executive Rob Crooke says.

"So, you have to shuffle them all around to get one new one in there."

By contrast, 3D XPoint works by changing the properties of the material that makes up its memory cells to either having a high resistance to electricity to represent a one or a low resistance to represent a zero.

The advantage is that each memory cell can be addressed individually, radically speeding things up.

An added benefit is that it should last hundreds of times longer than Nand before becoming unreliable.

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Scientists develop a memristor that can be conditioned just like a real synapse

An international collaboration of researchers from UMass Amherst, HP, and the Air Force have built a proof-of-concept memristor that could lead to real-world neuromorphic chips. The memristor is made of a silicon-oxygen-nitrogen material laced with clumps of silver nanoparticles at the electrical terminals. When current is applied across the memristor, the silver nanoparticles shuffle around within their parent oxynitride matrix, to line up within a lightning-bolt-like path of least electrical resistance. The electrical field exerts enough force on particles within a given radius of that path to scoot them subtly into line in the memristor’s ON state. The heat released by the electricity both permits and enables the movement.

If the memristor has been activated within a few seconds, it will still be in its ON state, with the silver nanoparticles still helpfully arranged into a nano-wire. This mimics short-term potentiation, which is an important kind of neuronal conditioning that we depend on for learning and memory. After a bunch of activations within a short period of time, silver drifts slowly toward one pole of the memristor and away from the other, mimicking desensitization (another form of classical conditioning) as calcium is depleted within the “tapped-out” upstream neuron. When the field is released and the memristor allowed to cool down and “rest,” those silver nanoparticles relax back to where they originally were, in discrete clumps around each electrode.
....
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Op zaterdag 29 oktober 2016 04:06 schreef crystal_meth het volgende:
Had dit bericht gemist bij m'n vorige post:

[..]

http://nanotechweb.org/cws/article/tech/66546

[..]

(een nonlinear selector is één waarin de stroom bvb exponentieel stijgt met de spanning. Dat vermindert de stroom door de sneak paths in verhouding tot de stroom door de geadresseerde cel, omdat over de cellen in de sneak paths slechts 1/3 van de aangelegde spanning staat)
Niet de eerste Self-rectifying memristor ("memristor met diodewerking"), in october 2014 was er bvb een bericht over een self-rectifying memristor met maximaal rectifying ratio van 600, die geschikt zou zijn voor een crossbar van maximaal 212*212 (voor een 10% read margin).

_{In m'n vorige post schreef ik dat een LED array geen last van sneak paths had omdat in elk sneak path één van de drie LEDs in sperzin staat; bij een memristor kan je niet simpelweg een diode toevoegen, omdat een memristor gereset (op 0 gezet) wordt door een negatieve spanning aan te leggen (het lezen gebeurt met een kleine positieve spanning/stroom, op 1 zetten met een hoge positieve spanning/stroom). Een normale diode laat haast geen stroom door in sperrichting, dus zou je de memristor niet kunnen resetten.}

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IBM scientists say radical new ‘in-memory’ computing architecture will speed up computers by 200 times

IBM Research announced Tuesday (Oct. 24, 2017) that its scientists have developed the first “in-memory computing” or “computational memory” computer system architecture, which is expected to yield yield 200x improvements in computer speed and energy efficiency — enabling ultra-dense, low-power, massively parallel computing systems.

Their concept is to use one device (such as phase change memory or PCM*) for both storing and processing information. That design would replace the conventional “von Neumann” computer architecture, used in standard desktop computers, laptops, and cellphones, which splits computation and memory into two different devices. That requires moving data back and forth between memory and the computing unit, making them slower and less energy-efficient.

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Op donderdag 26 oktober 2017 16:49 schreef Maanvis het volgende:
waarom hoop je dat digit2?

AlphaGo: the next generation

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Op vrijdag 27 oktober 2017 16:51 schreef Bosbeetle het volgende:

[..]

Ze zijn ook bezig om machine learning op quantum computers toe te passen, stond laast een interessante special in nature over quantum software, en wat de pitfalls zijn etc. We stappen zo langzamerhand in de computer wereld weer helemaal opnieuw in een groot avontuur. De eerste quantum computers met tientallen tot honderden qubits komen in zicht.

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Organic Memristor Sets Records for Speed and Durability

October 31

Modern electronic devices are based on circuit elements like resistors, capacitors, and inductors. However, there’s a fourth still-experimental type of component called a memristor. Engineers have been trying to perfect the memristor for years, but so far attempts to make these components a reality have failed on one or more fronts. However, a new organic memristor design from an international team of scientists could solve most of the outstanding problems and finally make these components commercially viable.

The memristor was first theorized in the early 1970s, but the technology of the day was not sophisticated enough to build one. A memristor is a two-terminal electrical component that has properties of both resistors and non-volatile memory. The electrical resistance isn’t constant, but changes based on the charge that has passed through the memristor in the past. That is, it remembers its history even if the power is shut off.

Past memristor designs in laboratories have failed in at least one of several ways. They were often too slow to switch states, or they just didn’t retain their memory for very long after the power was cut. The new organic memristor designed by a team of researchers led by Thirumalai Venky Venkatesan at the National University of Singapore is able to switch states in just 50 nanoseconds, similar to traditional resistors. It can also hold that state for more than 11 days without power.
The memristor is composed of the transition metal ruthenium complexed with “azo-aromatic ligands.” The theoretical work enabling this material was performed at Yale, and the organic molecules were synthesized at the Indian Association for the Cultivation of Sciences. Despite containing organic molecules, the memristors are very stable. No degradation of the on/off ratio after more than 10^12 read cycles. Venkatesan says this material is easy and cheap to make. None of the materials needed are particularly rare or dangerous, and fabrication techniques are based on existing technology.

There’s still a lot of work to be done before memristors will be ready for consumer devices, but the effects on daily life could be huge when that day arrives. Memristors could replace both storage and RAM with a single chip, and the capacity of memristor-based devices could be almost unfathomably huge. Some theoretical designs for multi-layer memristors have a storage capacity of 1 petabyte per cubic centimeter. Maybe spinning hard drives won’t be the capacity kings for as long as we thought.

Brain-Like (Neuromorphic) Computing - Computerphile

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Memristors, Artificial Synapses & Neomorphic Computing. Dr Phil Moriarty on the limitations of the Von Neumann architecture and what could be next.

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Op maandag 14 september 2020 15:27 schreef Maanvis het volgende:
Huh, ik zag die computerphile dinges voorbij komen maar ik had niet door dat het over de memristors ging. Maar eens kijken dan

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Op maandag 14 september 2020 16:26 schreef Maanvis het volgende:

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Is het net zoals kernfusie telkens 50 jaar totdat ie er komt?