De MEMRISTOR nieuw fundamenteel component

quote:

Use of porous silicon oxide reduces forming voltage, improves manufacturability

HOUSTON — (July 10, 2014) — Rice University’s breakthrough silicon oxide technology for high-density, next-generation computer memory is one step closer to mass production, thanks to a refinement that will allow manufacturers to fabricate devices at room temperature with conventional production methods.

This scanning electron microscope image and schematic show the design and composition of new RRAM memory devices based on porous silicon oxide that were created at Rice University. Credit: Tour Group/Rice University

First discovered five years ago, Rice’s silicon oxide memories are a type of two-terminal, “resistive random-access memory” (RRAM) technology. In a new paper available online in the American Chemical Society journal Nano Letters, a Rice team led by chemist James Tour compared its RRAM technology to more than a dozen competing versions.

“This memory is superior to all other two-terminal unipolar resistive memories by almost every metric,” Tour said. “And because our devices use silicon oxide — the most studied material on Earth — the underlying physics are both well-understood and easy to implement in existing fabrication facilities.” Tour is Rice’s T.T. and W.F. Chao Chair in Chemistry and professor of mechanical engineering and nanoengineering and of computer science.

Tour and colleagues began work on their breakthrough RRAM technology more than five years ago. The basic concept behind resistive memory devices is the insertion of a dielectric material — one that won’t normally conduct electricity — between two wires. When a sufficiently high voltage is applied across the wires, a narrow conduction path can be formed through the dielectric material.

This illustration depicts the rewriteable crystalline filament pathway in Rice University's porous silicon oxide RRAM memory devices. Credit: Tour Group/Rice University

The presence or absence of these conduction pathways can be used to represent the binary 1s and 0s of digital data. Research with a number of dielectric materials over the past decade has shown that such conduction pathways can be formed, broken and reformed thousands of times, which means RRAM can be used as the basis of rewritable random-access memory.

RRAM is under development worldwide and expected to supplant flash memory technology in the marketplace within a few years because it is faster than flash and can pack far more information into less space. For example, manufacturers have announced plans for RRAM prototype chips that will be capable of storing about one terabyte of data on a device the size of a postage stamp — more than 50 times the data density of current flash memory technology.

The key ingredient of Rice’s RRAM is its dielectric component, silicon oxide. Silicon is the most abundant element on Earth and the basic ingredient in conventional microchips. Microelectronics fabrication technologies based on silicon are widespread and easily understood, but until the 2010 discovery of conductive filament pathways in silicon oxide in Tour’s lab, the material wasn’t considered an option for RRAM.

Since then, Tour’s team has raced to further develop its RRAM and even used it for exotic new devices like transparent flexible memory chips. At the same time, the researchers also conducted countless tests to compare the performance of silicon oxide memories with competing dielectric RRAM technologies.

Rice University postdoctoral researcher Gunuk Wang, left, and chemist James Tour have demonstrated new techniques for using porous silicon oxide to make robust RRAM memory chips that can be easily manufactured with existing fabrication techniques. Credit: Jeff Fitlow/Rice University

“Our technology is the only one that satisfies every market requirement, both from a production and a performance standpoint, for nonvolatile memory,” Tour said. “It can be manufactured at room temperature, has an extremely low forming voltage, high on-off ratio, low power consumption, nine-bit capacity per cell, exceptional switching speeds and excellent cycling endurance.”

In the latest study, a team headed by lead author and Rice postdoctoral researcher Gunuk Wang showed that using a porous version of silicon oxide could dramatically improve Rice’s RRAM in several ways. First, the porous material reduced the forming voltage — the power needed to form conduction pathways — to less than two volts, a 13-fold improvement over the team’s previous best and a number that stacks up against competing RRAM technologies. In addition, the porous silicon oxide also allowed Tour’s team to eliminate the need for a “device edge structure.”

“That means we can take a sheet of porous silicon oxide and just drop down electrodes without having to fabricate edges,” Tour said. “When we made our initial announcement about silicon oxide in 2010, one of the first questions I got from industry was whether we could do this without fabricating edges. At the time we could not, but the change to porous silicon oxide finally allows us to do that.”

This electron microscope image shows the surface of the nanoporous silicon-oxide material used in Rice University's new RRAM memory devices. The red areas highlight gaps, or voids, in the material's amorphous silicon-oxide coating. Credit: Tour Group/Rice University

Wang said, “We also demonstrated that the porous silicon oxide material increased the endurance cycles more than 100 times as compared with previous nonporous silicon oxide memories. Finally, the porous silicon oxide material has a capacity of up to nine bits per cell that is highest number among oxide-based memories, and the multiple capacity is unaffected by high temperatures.”

Tour said the latest developments with porous silicon oxide — reduced forming voltage, elimination of need for edge fabrication, excellent endurance cycling and multi-bit capacity — are extremely appealing to memory companies.

“This is a major accomplishment, and we’ve already been approached by companies interested in licensing this new technology,” he said.

Study co-authors — all from Rice — include postdoctoral researcher Yang Yang; research scientist Jae-Hwang Lee; graduate students Vera Abramova, Huilong Fei and Gedeng Ruan; and Edwin Thomas, the William and Stephanie Sick Dean of Rice’s George R. Brown School of Engineering, professor in mechanical engineering and materials science and in chemical and biomolecular engineering.

quote:

Resistive RAM nears launch: Still the most likely candidate to replace NAND flash

December 22, 2014

It’s been a while since we checked in on Crossbar, the next-generation memory company working on a NAND flash replacement. The company’s resistive RAM (RRAM or ReRAM) technology stores data by creating resistance in a circuit rather than trapping electrons within a cell. Now, the company has announced that it’s moving towards commercializing its designs. That means it’s proven that it can build hardware at existing foundries and can seek vendors to bring solutions to market.

There are several intrinsic advantages to ReRAM as compared to NAND flash. NAND has limited endurance, its lifespan degrades as process nodes shrink and cells become smaller, and the amount of error-correction required at each new node is steadily increasing. Performance gains have slowed since clocking NAND faster also tends to cause it to degrade, and the bulk of improvements are now delivered by improving either the NAND controller or the system interface — not the underlying performance of the NAND itself.

ReRAM solves many of these problems. Unlike NAND, it doesn’t need to be erased before its programmed, and it’s much faster than NAND by multiple metrics. It also consumes less power — Crossbar claims that NAND requires 1360 picojoules per cell to program, while RRAM cuts this to just 64 picojoules per cell. Programming power is just one aspect to overall SSD power consumption, but the company also claims that its technology supports storing two bits of data per cell (analogous to MLC NAND) and can be stacked into 3D

The company also claims that its technology can be used to reduce the complexity of the microcontroller itself — a significant potential advantage as this is one area where complexity and cost have been increasing as the task of flash management becomes more complicated.

Commercialization of consumer hardware, however, remains some time away. Crossbar has demonstrated that its designs can scale up into the terascale, but that doesn’t mean it’s ready to bring products at that density to market.

The firm is now licensing to ASIC, FPGA, and SoC developers, with samples arriving in 2015. Early expected target applications are the embedded and low-level applications shown in the chart above, where very little storage is required and low-power operation is essential.

One thing that hasn’t changed is the long-term roadmap for actual NAND flash replacement. Here’s where the realities of economic scaling come home to roost. Samsung, Intel, Micron — these companies have invested tens of billions of dollars into NAND production, and they aren’t going to shift to a new standard on a dime. For all that the tech industry likes to pride itself on rapidly adopting the latest and greatest technology, the truth is far different — the most successful products in computing are those that extend previous work in a cost-effective manner. Come-from-behind overtake maneuvers are actually quite rare, which is one reason why storage mediums tend to live for decades even when faster solutions are available in the market.

Right now, 3D NAND flash (Samsung calls it V-NAND) will drive the market from at least 2015 to 2018. That doesn’t mean we won’t see RRAM in consumer or enterprise applications — the market has snapped up more-expensive NAND flash solutions that leverage standards like PCI Express or the upcoming NVMe, particularly when these products can enable faster response times for high-frequency stock trading or other latency-critical applications. RRAM may not “feel” much faster than NAND, but it has the potential to provide better response times at latencies that matter to computers, and that’s enough of a reason for certain segments to adopt the equipment.

Earlier this year, we covered advances in other NAND flash replacements, such as phase change memory (PCM). These designs have demonstrated substantially improved performance compared to NAND, but also face significant scaling challenges and cost concerns. RRAM uses conventional CMOS hardware and can operate at scales down to 5nm. NAND flash, in contrast, isn’t expected to scale below 10nm on even the most optimistic roadmaps, and it’s not certain it will even get that low.

3D NAND will extend this further by allowing companies to step back up to higher nodes (Samsung’s current V-NAND is built on 40nm process technology). It’s not necessarily fair to call that a stopgap when it could slap 5-10 years on NAND scaling, but it’s still a long-term functional limitation. We’re going to need to replace flash with some alternate form of memory in the long term if we want to continue to improve power consumption and scale compute capability upwards, and right now RRAM looks like the most practical near-term option.