[TK] 256MB PC133 SDRAM

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K4S560832C
CMOS SDRAM
256Mbit SDRAM
(Super low power)
8M x 8bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.5 Nov. 2001
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.5 Nov. 2001
K4S560832C
Revision History Revision 0.0 (Mar. 06, 2001) Revision 0.1 (Aug. 27, 2001)
· Add a new part number for the lower ICC6 support
CMOS SDRAM
Revision 0.2 (Sep., 2001)
· · Redefined IDD1 & IDD4 in DC Characteristics Changed the Notes in Operating AC Parameter. 5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. 5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Revision 0.3 (Oct., 2001)
· Redefined IDD6 from 1mA to 800uA in DC Characteristics
Revision 0.4 (Oct., 2001)
· Redefined IDD6 from 800uA to 700uA in DC Characteristics
Revision 0.5 (Nov., 2001)
· Redefined IDD6 from 700uA to 800uA in DC Characteristics
Rev. 0.5 Nov. 2001
K4S560832C
8M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
· JEDEC standard 3.3V power supply · LVTTL compatible with multiplexed address · Four banks operation · MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) · All inputs are sampled at the positive going edge of the system clock. · Burst read single-bit write operation · DQM for masking · Auto & self refresh · 64ms refresh period (8K Cycle) Part No. K4S560832C-TB7C K4S560832C-TB75 K4S560832C-TB1H K4S560832C-TB1L
CMOS SDRAM
GENERAL DESCRIPTION
The K4S560832C is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 8,392,608 words by 8bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Max Freq. 133MHz(CL=2) 133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL 54pin TSOP(II) Interface Package
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select 8M x 8 8M x 8 8M x 8 8M x 8 Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length
LR AS
LC BR
LCKE LRAS LCBR LWE LCAS
Programming Register LWCBR LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.5 Nov. 2001

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Op dinsdag 3 januari 2006 16:10 schreef outcast_within het volgende:
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Op dinsdag 3 januari 2006 16:15 schreef outcast_within het volgende:
zoals de wijze ellisaB zou zeggen. Game on

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Op dinsdag 3 januari 2006 16:16 schreef Het_Biertje het volgende:

[..]

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Op donderdag 5 januari 2006 09:58 schreef Sjabba het volgende:
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