De MEMRISTOR nieuw fundamenteel component

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Use of porous silicon oxide reduces forming voltage, improves manufacturability

HOUSTON — (July 10, 2014) — Rice University’s breakthrough silicon oxide technology for high-density, next-generation computer memory is one step closer to mass production, thanks to a refinement that will allow manufacturers to fabricate devices at room temperature with conventional production methods.

This scanning electron microscope image and schematic show the design and composition of new RRAM memory devices based on porous silicon oxide that were created at Rice University. Credit: Tour Group/Rice University

First discovered five years ago, Rice’s silicon oxide memories are a type of two-terminal, “resistive random-access memory” (RRAM) technology. In a new paper available online in the American Chemical Society journal Nano Letters, a Rice team led by chemist James Tour compared its RRAM technology to more than a dozen competing versions.

“This memory is superior to all other two-terminal unipolar resistive memories by almost every metric,” Tour said. “And because our devices use silicon oxide — the most studied material on Earth — the underlying physics are both well-understood and easy to implement in existing fabrication facilities.” Tour is Rice’s T.T. and W.F. Chao Chair in Chemistry and professor of mechanical engineering and nanoengineering and of computer science.

Tour and colleagues began work on their breakthrough RRAM technology more than five years ago. The basic concept behind resistive memory devices is the insertion of a dielectric material — one that won’t normally conduct electricity — between two wires. When a sufficiently high voltage is applied across the wires, a narrow conduction path can be formed through the dielectric material.

This illustration depicts the rewriteable crystalline filament pathway in Rice University's porous silicon oxide RRAM memory devices. Credit: Tour Group/Rice University

The presence or absence of these conduction pathways can be used to represent the binary 1s and 0s of digital data. Research with a number of dielectric materials over the past decade has shown that such conduction pathways can be formed, broken and reformed thousands of times, which means RRAM can be used as the basis of rewritable random-access memory.

RRAM is under development worldwide and expected to supplant flash memory technology in the marketplace within a few years because it is faster than flash and can pack far more information into less space. For example, manufacturers have announced plans for RRAM prototype chips that will be capable of storing about one terabyte of data on a device the size of a postage stamp — more than 50 times the data density of current flash memory technology.

The key ingredient of Rice’s RRAM is its dielectric component, silicon oxide. Silicon is the most abundant element on Earth and the basic ingredient in conventional microchips. Microelectronics fabrication technologies based on silicon are widespread and easily understood, but until the 2010 discovery of conductive filament pathways in silicon oxide in Tour’s lab, the material wasn’t considered an option for RRAM.

Since then, Tour’s team has raced to further develop its RRAM and even used it for exotic new devices like transparent flexible memory chips. At the same time, the researchers also conducted countless tests to compare the performance of silicon oxide memories with competing dielectric RRAM technologies.

Rice University postdoctoral researcher Gunuk Wang, left, and chemist James Tour have demonstrated new techniques for using porous silicon oxide to make robust RRAM memory chips that can be easily manufactured with existing fabrication techniques. Credit: Jeff Fitlow/Rice University

“Our technology is the only one that satisfies every market requirement, both from a production and a performance standpoint, for nonvolatile memory,” Tour said. “It can be manufactured at room temperature, has an extremely low forming voltage, high on-off ratio, low power consumption, nine-bit capacity per cell, exceptional switching speeds and excellent cycling endurance.”

In the latest study, a team headed by lead author and Rice postdoctoral researcher Gunuk Wang showed that using a porous version of silicon oxide could dramatically improve Rice’s RRAM in several ways. First, the porous material reduced the forming voltage — the power needed to form conduction pathways — to less than two volts, a 13-fold improvement over the team’s previous best and a number that stacks up against competing RRAM technologies. In addition, the porous silicon oxide also allowed Tour’s team to eliminate the need for a “device edge structure.”

“That means we can take a sheet of porous silicon oxide and just drop down electrodes without having to fabricate edges,” Tour said. “When we made our initial announcement about silicon oxide in 2010, one of the first questions I got from industry was whether we could do this without fabricating edges. At the time we could not, but the change to porous silicon oxide finally allows us to do that.”

This electron microscope image shows the surface of the nanoporous silicon-oxide material used in Rice University's new RRAM memory devices. The red areas highlight gaps, or voids, in the material's amorphous silicon-oxide coating. Credit: Tour Group/Rice University

Wang said, “We also demonstrated that the porous silicon oxide material increased the endurance cycles more than 100 times as compared with previous nonporous silicon oxide memories. Finally, the porous silicon oxide material has a capacity of up to nine bits per cell that is highest number among oxide-based memories, and the multiple capacity is unaffected by high temperatures.”

Tour said the latest developments with porous silicon oxide — reduced forming voltage, elimination of need for edge fabrication, excellent endurance cycling and multi-bit capacity — are extremely appealing to memory companies.

“This is a major accomplishment, and we’ve already been approached by companies interested in licensing this new technology,” he said.

Study co-authors — all from Rice — include postdoctoral researcher Yang Yang; research scientist Jae-Hwang Lee; graduate students Vera Abramova, Huilong Fei and Gedeng Ruan; and Edwin Thomas, the William and Stephanie Sick Dean of Rice’s George R. Brown School of Engineering, professor in mechanical engineering and materials science and in chemical and biomolecular engineering.

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Resistive RAM nears launch: Still the most likely candidate to replace NAND flash

December 22, 2014

It’s been a while since we checked in on Crossbar, the next-generation memory company working on a NAND flash replacement. The company’s resistive RAM (RRAM or ReRAM) technology stores data by creating resistance in a circuit rather than trapping electrons within a cell. Now, the company has announced that it’s moving towards commercializing its designs. That means it’s proven that it can build hardware at existing foundries and can seek vendors to bring solutions to market.

There are several intrinsic advantages to ReRAM as compared to NAND flash. NAND has limited endurance, its lifespan degrades as process nodes shrink and cells become smaller, and the amount of error-correction required at each new node is steadily increasing. Performance gains have slowed since clocking NAND faster also tends to cause it to degrade, and the bulk of improvements are now delivered by improving either the NAND controller or the system interface — not the underlying performance of the NAND itself.

ReRAM solves many of these problems. Unlike NAND, it doesn’t need to be erased before its programmed, and it’s much faster than NAND by multiple metrics. It also consumes less power — Crossbar claims that NAND requires 1360 picojoules per cell to program, while RRAM cuts this to just 64 picojoules per cell. Programming power is just one aspect to overall SSD power consumption, but the company also claims that its technology supports storing two bits of data per cell (analogous to MLC NAND) and can be stacked into 3D

The company also claims that its technology can be used to reduce the complexity of the microcontroller itself — a significant potential advantage as this is one area where complexity and cost have been increasing as the task of flash management becomes more complicated.

Commercialization of consumer hardware, however, remains some time away. Crossbar has demonstrated that its designs can scale up into the terascale, but that doesn’t mean it’s ready to bring products at that density to market.

The firm is now licensing to ASIC, FPGA, and SoC developers, with samples arriving in 2015. Early expected target applications are the embedded and low-level applications shown in the chart above, where very little storage is required and low-power operation is essential.

One thing that hasn’t changed is the long-term roadmap for actual NAND flash replacement. Here’s where the realities of economic scaling come home to roost. Samsung, Intel, Micron — these companies have invested tens of billions of dollars into NAND production, and they aren’t going to shift to a new standard on a dime. For all that the tech industry likes to pride itself on rapidly adopting the latest and greatest technology, the truth is far different — the most successful products in computing are those that extend previous work in a cost-effective manner. Come-from-behind overtake maneuvers are actually quite rare, which is one reason why storage mediums tend to live for decades even when faster solutions are available in the market.

Right now, 3D NAND flash (Samsung calls it V-NAND) will drive the market from at least 2015 to 2018. That doesn’t mean we won’t see RRAM in consumer or enterprise applications — the market has snapped up more-expensive NAND flash solutions that leverage standards like PCI Express or the upcoming NVMe, particularly when these products can enable faster response times for high-frequency stock trading or other latency-critical applications. RRAM may not “feel” much faster than NAND, but it has the potential to provide better response times at latencies that matter to computers, and that’s enough of a reason for certain segments to adopt the equipment.

Earlier this year, we covered advances in other NAND flash replacements, such as phase change memory (PCM). These designs have demonstrated substantially improved performance compared to NAND, but also face significant scaling challenges and cost concerns. RRAM uses conventional CMOS hardware and can operate at scales down to 5nm. NAND flash, in contrast, isn’t expected to scale below 10nm on even the most optimistic roadmaps, and it’s not certain it will even get that low.

3D NAND will extend this further by allowing companies to step back up to higher nodes (Samsung’s current V-NAND is built on 40nm process technology). It’s not necessarily fair to call that a stopgap when it could slap 5-10 years on NAND scaling, but it’s still a long-term functional limitation. We’re going to need to replace flash with some alternate form of memory in the long term if we want to continue to improve power consumption and scale compute capability upwards, and right now RRAM looks like the most practical near-term option.

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3D Xpoint memory: Faster-than-flash storage unveiled

A new kind of memory technology is going into production, which is up to 1,000 times faster than the Nand flash storage used in memory cards and computers' solid state drives (SSDs).

The innovation is called 3D XPoint, and is the invention of Intel and Micron.

The two US companies predict a wide range of benefits, from speeding up scientific research to making more elaborate video games.

One expert described it as a "huge step forward".

"There are other companies who have talked about new types of memory technology, but this is about being able to manufacture the stuff - that's why they are making such a big deal out of it," says Bob O'Donnell, from the consultancy Technalysis.
If all goes to plan, the first products to feature 3D XPoint (pronounced cross-point) will go on sale next year. Its price has yet to be announced.

Intel is marketing it as the first new class of "mainstream memory" since 1989.

Rather than pitch it as a replacement for either flash storage or RAM (random access memory), the company suggests it will be used alongside them to hold certain data "closer" to a processor so that it can be accessed more quickly than before.
So, what's the big advantage over flash memory?

3D XPoint does away with the need to use the transistors at the heart of Nand chips.

Nand works by moving electrons back and forth to an isolated part of the transistors known as their "floating gates" to represent the ones and zeros of binary code.

An issue with this technique is that it cannot rewrite single bits of data at a time. Instead, larger blocks of information have to be wiped and then rewritten to incorporate the changes.

"It's kind of like a parking lot where you want to move one of the cars, but they are all jammed in," Intel executive Rob Crooke says.

"So, you have to shuffle them all around to get one new one in there."

By contrast, 3D XPoint works by changing the properties of the material that makes up its memory cells to either having a high resistance to electricity to represent a one or a low resistance to represent a zero.

The advantage is that each memory cell can be addressed individually, radically speeding things up.

An added benefit is that it should last hundreds of times longer than Nand before becoming unreliable.

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Scientists develop a memristor that can be conditioned just like a real synapse

An international collaboration of researchers from UMass Amherst, HP, and the Air Force have built a proof-of-concept memristor that could lead to real-world neuromorphic chips. The memristor is made of a silicon-oxygen-nitrogen material laced with clumps of silver nanoparticles at the electrical terminals. When current is applied across the memristor, the silver nanoparticles shuffle around within their parent oxynitride matrix, to line up within a lightning-bolt-like path of least electrical resistance. The electrical field exerts enough force on particles within a given radius of that path to scoot them subtly into line in the memristor’s ON state. The heat released by the electricity both permits and enables the movement.

If the memristor has been activated within a few seconds, it will still be in its ON state, with the silver nanoparticles still helpfully arranged into a nano-wire. This mimics short-term potentiation, which is an important kind of neuronal conditioning that we depend on for learning and memory. After a bunch of activations within a short period of time, silver drifts slowly toward one pole of the memristor and away from the other, mimicking desensitization (another form of classical conditioning) as calcium is depleted within the “tapped-out” upstream neuron. When the field is released and the memristor allowed to cool down and “rest,” those silver nanoparticles relax back to where they originally were, in discrete clumps around each electrode.
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Op zaterdag 29 oktober 2016 04:06 schreef crystal_meth het volgende:
Had dit bericht gemist bij m'n vorige post:

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http://nanotechweb.org/cws/article/tech/66546

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(een nonlinear selector is één waarin de stroom bvb exponentieel stijgt met de spanning. Dat vermindert de stroom door de sneak paths in verhouding tot de stroom door de geadresseerde cel, omdat over de cellen in de sneak paths slechts 1/3 van de aangelegde spanning staat)
Niet de eerste Self-rectifying memristor ("memristor met diodewerking"), in october 2014 was er bvb een bericht over een self-rectifying memristor met maximaal rectifying ratio van 600, die geschikt zou zijn voor een crossbar van maximaal 212*212 (voor een 10% read margin).

_{In m'n vorige post schreef ik dat een LED array geen last van sneak paths had omdat in elk sneak path één van de drie LEDs in sperzin staat; bij een memristor kan je niet simpelweg een diode toevoegen, omdat een memristor gereset (op 0 gezet) wordt door een negatieve spanning aan te leggen (het lezen gebeurt met een kleine positieve spanning/stroom, op 1 zetten met een hoge positieve spanning/stroom). Een normale diode laat haast geen stroom door in sperrichting, dus zou je de memristor niet kunnen resetten.}

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IBM scientists say radical new ‘in-memory’ computing architecture will speed up computers by 200 times

IBM Research announced Tuesday (Oct. 24, 2017) that its scientists have developed the first “in-memory computing” or “computational memory” computer system architecture, which is expected to yield yield 200x improvements in computer speed and energy efficiency — enabling ultra-dense, low-power, massively parallel computing systems.

Their concept is to use one device (such as phase change memory or PCM*) for both storing and processing information. That design would replace the conventional “von Neumann” computer architecture, used in standard desktop computers, laptops, and cellphones, which splits computation and memory into two different devices. That requires moving data back and forth between memory and the computing unit, making them slower and less energy-efficient.

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Op donderdag 26 oktober 2017 16:49 schreef Maanvis het volgende:
waarom hoop je dat digit2?

AlphaGo: the next generation

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Op vrijdag 27 oktober 2017 16:51 schreef Bosbeetle het volgende:

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Ze zijn ook bezig om machine learning op quantum computers toe te passen, stond laast een interessante special in nature over quantum software, en wat de pitfalls zijn etc. We stappen zo langzamerhand in de computer wereld weer helemaal opnieuw in een groot avontuur. De eerste quantum computers met tientallen tot honderden qubits komen in zicht.

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Organic Memristor Sets Records for Speed and Durability

October 31

Modern electronic devices are based on circuit elements like resistors, capacitors, and inductors. However, there’s a fourth still-experimental type of component called a memristor. Engineers have been trying to perfect the memristor for years, but so far attempts to make these components a reality have failed on one or more fronts. However, a new organic memristor design from an international team of scientists could solve most of the outstanding problems and finally make these components commercially viable.

The memristor was first theorized in the early 1970s, but the technology of the day was not sophisticated enough to build one. A memristor is a two-terminal electrical component that has properties of both resistors and non-volatile memory. The electrical resistance isn’t constant, but changes based on the charge that has passed through the memristor in the past. That is, it remembers its history even if the power is shut off.

Past memristor designs in laboratories have failed in at least one of several ways. They were often too slow to switch states, or they just didn’t retain their memory for very long after the power was cut. The new organic memristor designed by a team of researchers led by Thirumalai Venky Venkatesan at the National University of Singapore is able to switch states in just 50 nanoseconds, similar to traditional resistors. It can also hold that state for more than 11 days without power.
The memristor is composed of the transition metal ruthenium complexed with “azo-aromatic ligands.” The theoretical work enabling this material was performed at Yale, and the organic molecules were synthesized at the Indian Association for the Cultivation of Sciences. Despite containing organic molecules, the memristors are very stable. No degradation of the on/off ratio after more than 10^12 read cycles. Venkatesan says this material is easy and cheap to make. None of the materials needed are particularly rare or dangerous, and fabrication techniques are based on existing technology.

There’s still a lot of work to be done before memristors will be ready for consumer devices, but the effects on daily life could be huge when that day arrives. Memristors could replace both storage and RAM with a single chip, and the capacity of memristor-based devices could be almost unfathomably huge. Some theoretical designs for multi-layer memristors have a storage capacity of 1 petabyte per cubic centimeter. Maybe spinning hard drives won’t be the capacity kings for as long as we thought.

Brain-Like (Neuromorphic) Computing - Computerphile

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Memristors, Artificial Synapses & Neomorphic Computing. Dr Phil Moriarty on the limitations of the Von Neumann architecture and what could be next.

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Op maandag 14 september 2020 15:27 schreef Maanvis het volgende:
Huh, ik zag die computerphile dinges voorbij komen maar ik had niet door dat het over de memristors ging. Maar eens kijken dan

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Op maandag 14 september 2020 16:26 schreef Maanvis het volgende:

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Is het net zoals kernfusie telkens 50 jaar totdat ie er komt?

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Wir produzieren immer mehr Daten. Und das Ganze, das wächst auch noch exponentiell an! Bis 2030 soll der Strombedarf von Rechenzentren auf 945 Terrawattstunden ansteigen. Das ist einfach das doppelte unseres Stromverbrauchs in Deutschland. Etwa 90 % der Energie fallen für den Transport zwischen Speicher und Prozessor an.
Aber man kann etwas dagegen machen: Sogenannte neuromorphe Chips. Die verarbeiten die Daten dort, wo sie gespeichert werden. Und das spart nicht nur Energie, sondern das ist sogar bis zu 400-mal schneller. Ich war in der Nähe von Dresden bei einem Unternehmen, was genau diese Chips entwickelt und herstellt und habe mir angeschaut, wie das Ganze funktioniert, wo es schon eingesetzt wird und natürlich auch, was das Potenzial für die Zukunft ist.